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p-dso-20-12 7 a h-bridge for dc-motor applications preliminary data sheet tle 6209 r preliminary data sheet, version 2.0 1 2001-03-14 1 overview 1.1 features ? delivers up to 6 a continuous and 7 a peak current optimized for dc motor management applications very low r ds on of typ. 150 m ? @25 c per switch operates at supply voltages of up to 40v overvoltage protection against transients up to 45 v outputs fully short circuit protected standard spi-interface, daisy chain capability adjustable chopper current regulation of up to 7 a temperature monitor with prewarning, warning and shutdown over- and undervoltage-lockout open load detection detailed load failure diagnosis by spi minimized power dissipation due to active free-wheeling low emi due to voltage slope regulation very low current consumption (typ. 20 a @ 25 c) in stand-by (inhibit) mode enhanced power p-dso-package functional description the tle 6209 r is an integrated power h-bridge with d-mos output stages for driving bidirectional loads such as dc-motors. the design is based on infineons smart power technology spt which allows bipolar, cmos and power d-mos devices on the same monolithic circuit. operation modes forward (cw), reverse (ccw) and brake are invoked by two control pins pwm and dir. protection and a reliable diagnosis of overcurrent, openload, short-circuit to ground, to the supply voltage or across the load are integrated. detailed diagnostic information is given via the 8 bit spi status word. an integrated chopper current limitation limits the current e.g. to reduce power dissipation during mechanical block of a dc type ordering code package tle 6209 r on request p-dso-20-12
tle 6209 r preliminary data sheet, version 2.0 2 2001-03-14 motor. several device parameters can be set by the spi control word. a three-level temperature monitoring with prewarning, warning and shutdown is included for controlled operation under critical power loss conditions. the full protection and diagnosis capability make the device suitable especially for safety relevant applications, e.g. in automotive ecus. 1.2 pin configuration (top view) pin definitions and functions v s power supply voltage v cc 5 v logic supply drv input for charge pump buffer capacitor gnd ground sdi serial data input sdo serial data output sclk serial clock input csn chip-select-not input out power output ? ? pwm pwm input dir direction input dis disable input inh inhibit tle 6209 r inh gnd v s gnd out 2 v cc gnd gnd csn out 1 1 7 6 5 4 3 2 10 9 8 20 14 15 16 17 18 19 11 12 13 sclk sdi sdo drv out 1 out 2 v s pwm dir dis
tle 6209 r preliminary data sheet, version 2.0 3 2001-03-14 1.2.1 pin definitions and functions pin no. symbol function 1, 10, 11, 20 gnd ground; internally connected to cooling tab (heat slug); to reduce thermal resistance place cooling areas and thermal vias on pcb. 2,3 out1 output 1 ; output of d-mos half bridge 1; external connection between pin 2 and pin 3 is necessary. 4,17 v s power supply ; needs a blocking capacitor as close as possible to gnd; 47 f electrolytic in parallel to 220 nf ceramic is recommended; external connection between pin 4 and pin 17 is necessary. 5sclk serial clock input ; clocks the shiftregister; sclk has an internal active pull down and requires cmos logic levels 6sdi serial data input; receives serial data from the control device; serial data transmitted to sdi is an 8 bit control word with the least significant bit (lsb) being transferred first; the input has an active pull down and requires cmos logic levels; sdi will accept data on the falling edge of sclk-signal; see table 1 for input data protocol. 7sdo serial-data-output; this tri-state output transfers diagnosis data to the control device; the output will remain tri-stated unless the device is selected by a low on chip-select-not (csn); sdo state changes on the rising edge of sclk; see table 4 for diagnosis protocol. 8csn chip-select-not input ; csn is an active low input; serial communication is enabled by pulling the csn terminal low; csn input should only be transitioned when sclk is low; csn has an internal active pull up and requires cmos logic levels. 9inh inhibit input; has an internal pull down; device is switched in standby condition by pulling the inh terminal low. 12 dis disable input; has an internal pull up; the output stages are switched in tristate condition by pulling the dis terminal high. 13 dir direction input; ttl/cmos compatible input. 14 pwm pwm input; ttl/cmos compatible input. 15 v cc logic supply voltage ; needs a blocking capacitor as close as possible to gnd; 10 f electrolytic in parallel to 220 nf ceramic is recommended. 16 drv drive; input for external charge pump capacitor c drv 18,19 out2 output 2 ; output of d-mos half bridge 2; external connection between pin 2 and pin 3 is necessary.
tle 6209 r preliminary data sheet, version 2.0 4 2001-03-14 1.3 functional block diagram figure 1 block diagram bias inhibit charge pump s p i uv ov tsd fault- detect 1 v cc inh sclk sdo sdi csn drv pwm dir v s gnd out 2 out 1 dis driver & gate- control 1,10,11,20 16 15 4,17 2,3 18,19 14 13 7 5 6 8 12 9 direct input 8 bit logic and latch
tle 6209 r preliminary data sheet, version 2.0 5 2001-03-14 2 circuit description 2.1 serial peripheral interface (spi) the spi is used for bidirectional communication with a control unit. the 8-bit programming word or control word (see table 1 ) is read in via the sdi serial data input, and this is synchronized with the serial clock input sclk. the status word appears synchronously at the sdo serial data output (see table 4 ). the transmission cycle begins when the chip is selected with the chip-select-not (csn) input (h to l). when the csn input changes from l to h, the word which has been read into the shift register becomes the control word. the sdo output switches then to tristate status, thereby releasing the sdo bus circuit for other uses. the spi allows to parallel multiple spi devices by using multiple csn lines. due to the full duplex shift register, the tle 6209 r can also be used in daisy-chain configuration. the settings made by the spi control word become active at the end of the spi transmission and remain valid until a different control word is transmitted or a power on reset occurs. at each spi transmission, the diagnosis bits as currently valid in the error logic are transmitted. the behavior of the diagnosis bits is described in section 2.5 . table 1 input data protocol bit 7 status register reset: h = reset 6 ovlo: h = on, l = off 5 not used 4 msb of 2bit chopper-off-time 3 lsb of 2bit chopper-off-time 2 pwm operation mode: h = fast decay, l = slow decay 1 msb of 2 bit chopper current limit 0 lsb of 2 bit chopper current limit
tle 6209 r preliminary data sheet, version 2.0 6 2001-03-14 table 2 programmable chopper current limit i l_xx bit 1 bit 0 current limit 00 i l_00 01 i l_01 10 i l_10 11 i l_11 note: for actual values, see page 16 table 3 programmable chopper off-time t off_xx bit 4 bit 3 chopper-off-time 00 t off_00 01 t off_01 10 t off_10 11 t off_11 note: for actual values, see page 16 table 4 diagnosis data protocol bit h = error/l = no error 7 power supply fail 6 not used, always h 5short to v s or across the load 4 short to gnd 3 open load 2 msb of temperature monitoring 1 lsb of temperature monitoring 0error-flag table 5 temperature monitoring bit 2 bit 1 chip temperature 0 0 below prewarning 0 1 temperature prewarning
tle 6209 r preliminary data sheet, version 2.0 7 2001-03-14 2.2 supply 2.2.1 logic supply voltage, power-on-reset the logic is supplied with 5 v by the v cc pin, separated from the power stage supply v s . the advantage of this system is that information stored in the logic remains intact even in the event of failures in the supply voltage v s . the power supply failure information can be read out via the spi. if v cc falls below typically 4.5 v, the logic is shut down, all internally stored data is deleted and the output stages are switched to tristate. the ic is restarted on rising v cc with a hysteresis of typically 80 mv after this restart at increasing v cc , or if the device is activated after having been set into inhibit mode (inh l to h), the ic is initialized by power-on-reset (por). after por, all spi control bits are set to l. this setting remains valid until first spi communication. also the error bits are reset by por. 2.2.2 power supply voltage the power stages are connected to the supply voltage v s . this voltage is monitored by over voltage (ov) and under voltage (uv) comparators as described in section 2.5.6 . the power supply voltage needs a blocking capacitor to gnd. 2.3 direct inputs 2.3.1 inhibit (sleep mode) the inh input can be used to cut off the complete ic. by pulling the inh input to low, the power stages are switched to tristate, and the current consumption is reduced to just a few a at both the v s and the v cc input. it also leads to the loss of any data stored. the tle 6209 r is reinitialized with por if inh is put to high again. the pin has an internal pull-down. 2.3.2 disable the dis input can be used to disable the output stages. by pulling the dis input to high the power stages are switched to tristate, regardless of the signals at the dir and pwm inputs. the dis input can be used as an emergency disable without resetting the spi data stored in the ic. it has an internal pull-up. 1 0 temperature warning 1 1 overtemperature shutdown table 5 temperature monitoring bit 2 bit 1 chip temperature
tle 6209 r preliminary data sheet, version 2.0 8 2001-03-14 2.3.3 direction and pwm the power stages are controlled by the direct inputs dir and pwm as given in table 6 and further illustrated in figure 2 . the dir input gives the direction of output current, while the pwm input controls whether the current is increased or reduced. the spi control bit 2 sets the decay mode, i.e. determines what happens if pwm = l. in pulse- width modulated applications, this control scheme allows to supply the pwm-signal always through the same port, using less controller resources. figure 2 dir/pwm control with slow- and fast decay table 6 functional truth table dir pwm mode (bit 2) out1 out2 comments 01 0 (slow decay) h l motor turns clockwise 0 0 h h freewheel with slow decay 1 1 l h motor turns counterclockwise 1 0 h h freewheel with slow decay 01 1 (fast decay) h l motor turns clockwise 0 0 l h fast decay 1 1 l h motor turns counterclockwise 1 0 h l fast decay m m pwm = h pwm = l m m pwm = h pwm = l slow decay fast decay
tle 6209 r preliminary data sheet, version 2.0 9 2001-03-14 2.4 power stages the output stages consist of a dmos h-bridge built by two highside switches and two lowside switches. integrated circuits protect the outputs against overcurrent and overtemperature if there is a short-circuit to ground or to the supply voltage or across the load. positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes. 2.4.1 charge pump to realize the fast switching times, the charge pump, which generates the voltage necessary to switch on the n-channel d-mos high-side switches, must be highly efficient. it requires an external capacitor c drv which is connected to v s and the charge pump buffer input, drv. it should be placed as close to the pins as possible. 2.4.2 chopper current limitation to limit the output current, a chopper current limitation is integrated as shown in figure 3 . the current is measured by sense cells integrated in the low-side switches. as soon the current limit i l is reached, the low-side switch is switched off for a fixed time t off . i l and t off can be set by the spi control bits 0,1, 3 and 4. figure 3 chopper current limitation 2.4.3 active freewheeling when drivng inductive loads with pwm operation, the dissipated power can be significantly reduced by activating the transistor located parallel to the internal freewheeling diode. this is realized in the tle 6209 r. when switching an output from l to h, the high-side switch is turned on after a certain dead-time to avoid cross currents flowing through the half bridge. i out current limit i l off-time t off time
tle 6209 r preliminary data sheet, version 2.0 10 2001-03-14 2.5 protection and diagnosis 2.5.1 short of output to ground the high-side switches are protected against a short of the output to ground by an over current shutdown. if a high-side switch is turned on and the current rises above the high- side shutdown threshold i sdh for longer than the shutdown delay time t doc , all output transistors are turned off and bit 4 the spi diagnosis word is set. during the delay time, the current is limited to i sc (typically 20 a). the output stages stay off and the error bit set until a status register reset (bit 7 of spi control word) is received or a power-on reset is performed. 2.5.2 short of output to v s due to the chopper current regulation, the low-side switches are protected against a short to the supply voltage. to detect the short, the first time the current limit is reached, the off-command for the low-side switch is blanked out for 10 s. if the current rises above the low-side shutdown threshold i sdl during this time, all output transistors are turned off and bit 5 in the spi diagnosis word is set. the value of the shutdown threshold depends on the current limit that is set via the spi. the shutdown threshold is 1 a higher than the current limit. the output stages stay off and the error bit set until a status register reset (bit 7 of spi control word) is received or a power-on reset is performed. 2.5.3 short across the load the short circuit protection circuits of the high- and low-side switches work independently of each other. in most cases, a short across the load will be detected as a short to v s because of the longer filter time in the high-side switches t doc and the higher shutdown threshold i sdh . 2.5.4 open load if the current through the low side transistor is lower than the reference current i dol in on-state (pwm = h), a timer is started. after a filter time t doc an open load failure will be recognized and the status bit 3 is set. if the current exceeds the reference current i dol the open load timer is reset. if the h-bridge is switched to off-state (pwm = l) the timer is stopped but not reset. the timer continues if the h-bridge is switched to on-state again. there is no reset of the open load timer if the direction is changed using the dir input in open load condition. the open load error bit is latched and can be reset by the status register reset bit 7 of the spi control word or a por. 2.5.5 temperature monitoring temperature sensors are integrated in the power stages. the temperature monitoring circuit compares the measured temperature to the prewarning, warning and shutdown
tle 6209 r preliminary data sheet, version 2.0 11 2001-03-14 thresholds. as soon as a threshold is reached, the according status bits are set in the spi diagnosis word (c.f. table 5 ). if the overtemperature shutdown threshold is reached, the output stages are turned off. the temperature monitoring messages and the over temperature shutdown are latched and can be reset by the status register reset bit 7 of the spi control word or a por. 2.5.6 power supply fail the power supply voltage is monitored for over- and under voltage lockout: under voltage lockout if the supply voltage v s drops below the switch off voltage v uv off , all output transistors are switched off and the power supply fail bit (bit 7 of the spi diagnosis word) is set. if v s rises again and reaches the switch on voltage v uv on , the power stages are restarted. the error bit, however, is latched and has to be reset by the status register reset bit 7 of the spi control word. over voltage lockout if the supply voltage v s rises above the switch off voltage v ov off , all output transistors are switched off and the power supply fail bit (bit 7 of the spi diagnosis word) is set. if v s falls again and reaches the switch on voltage v ov on , the power stages are restarted. the error bit, however, is latched and has to be reset by the status register reset bit 7 of the spi control word. the ovlo is only active if control bit 6 is h. if the bit is low, the ovlo is deactivated. 2.5.7 error flag bit 0 of the spi diagnosis word is an or of the status bits 1 to 7. it can be read out without full spi communication as described in figure 8 .
tle 6209 r preliminary data sheet, version 2.0 12 2001-03-14 3 characteristics note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.1 absolute maximum ratings parameter symbol limit values unit remarks min. max. voltages supply voltage v s ? 0.3 40 v ? supply voltage v s ? 145 v t < 0.5 s; i s > ? 2 a logic supply voltage v cc ? 0.3 5.5 v 0 v < v s < 40 v logic input voltages (sdi, sclk, csn, inh, dis, pwm, dir) v i ? 0.3 5.5 v 0 v < v s < 40 v 0 v < v cc < 5.5 v logic output voltage (sdo) v o ? 0.3 5.5 v 0 v < v s < 40 v 0 v < v cc < 5.5 v output voltage (out1, out2) v out ? 0.3 v v s + 1,5v ? 0 v < v s < 40 v charge pump buffer voltage (drv) v drv v s ? 0.3 v v s + 15 v ? 0 v < v s < 40 v currents output current (cont.) i out ?? a internally limited, see page 16 and page 17. output current (peak) i out ?? a temperatures junction temperature t j ? 40 150 c ? storage temperature t stg ? 50 150 c ?
tle 6209 r preliminary data sheet, version 2.0 13 2001-03-14 3.2 operating range parameter symbol limit values unit remarks min. max. supply voltage v s v uv off 40 v after v s rising above v uv on supply voltage slew rate d v s /d t ? 10 10 v/ s ? logic supply voltage v cc 4.75 5.50 v ? supply voltage increasing v s ? 0.3 v uv on v outputs in tristate supply voltage decreasing v s ? 0.3 v uv off v outputs in tristate logic input voltage (sdi, sclk, csn, inh) v i ? 0.3 v cc v ? spi clock frequency f clk ? 2mhz ? junction temperature t j ? 40 150 c ? thermal resistances junction pin r thjc ? 1.5 k/w measured to pin 1, 10, 11, 20 junction ambient r thja ? 50 k/w ?
tle 6209 r preliminary data sheet, version 2.0 14 2001-03-14 3.3 electrical characteristics 8 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test conditions min. typ. max. current consumption quiescent current i s ?? 50 a inh = low; v s = 13.2 v quiescent current i s ? 10 30 a inh = low; v s = 13.2 v; t j = 25 c logic-supply current i cc ?? 20 a inh = low logic-supply current i cc ? 26.0ma ? supply current i s ? 2.8 5 ma ? over- and under-voltage lockout uv-switch-on voltage v uv on ? 5.4 5.7 v v s increasing uv-switch-off voltage v uv off 4.0 4.9 5.2 v v s decreasing uv-on/off-hysteresis v uv hy 0.2 0.5 ? v v uv on ? v uv off ov-switch-off voltage v ov off 34 37 40 v v s increasing ov-switch-on voltage v ov on 28 32 36 v v s decreasing ov-on/off-hysteresis v ov hy ? 5.0 ? v v ov off ? v ov on
tle 6209 r preliminary data sheet, version 2.0 15 2001-03-14 outputs out1-2 static drain-source-on resistance source (high-side) i out = ? 3a r ds on h ? 140 170 m ? 5.2 v < v s < 40 v t j = 25 c; c drv = 33 nf ? 300 m ? 5.2 v < v s < 40 v c drv = 33 nf sink (low-side) i out = 3 a r ds on l ? 130 160 m ? 5.2 v < v s < 40 v t j = 25 c; c drv = 33 nf ? 300 m ? 5.2 v < v s < 40 v c drv = 33 nf clamp diodes forward voltage upper v fu ? 1.0 1.5 v i f = 3 a lower v fl ? 1.0 1.5 v i f = 3 a 3.3 electrical characteristics (cont ? d) 8 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test conditions min. typ. max.
tle 6209 r preliminary data sheet, version 2.0 16 2001-03-14 open circuit/underload detection detection current i ocd 40 ? 150 ma ? delay time t doc 2 ? 8ms ? current limits current limit i l_00 3.4 4 4.6 a bit 0 = l; bit 1 = l; current limit i l_01 4.25 5 5.75 a bit 0 = h; bit 1 = l; current limit i l_10 5.1 6 6.9 a bit 0 = l; bit 1 = h; current limit i l_11 5.95 7 8.05 a bit 0 = h; bit 1 = h; switch-off time during current limitation (chopper off-time) off-time t off_00 16 24 28 s bit 3 = l; bit 4 = l; off-time t off_01 32 43 51 sbit 3 = h; bit 4 = l; off-time t off_10 48 62 74 s bit 3 = l; bit 4 = h; off-time t off_11 64 80 96 sbit 3 = h; bit 4 = h; 3.3 electrical characteristics (cont ? d) 8 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test conditions min. typ. max.
tle 6209 r preliminary data sheet, version 2.0 17 2001-03-14 high-side switch overcurrent high-side shutdown threshold i sdh 81218a ? shutdown delay time t dsd t.b.d. 20 t.b.d s sink and source short circuit current i sc ?? 25 a during t dsd note: for short circuit current definition, see figure 5 . short circuit current is guaranteed by design leakage current / output current in tristate source-output-stage i qlh ? 200 ?? a v out = 0 v sink-output-stage i qll ?? 1ma v out = v s output delay times (device not in stand-by for t > 1 ms) high-side on t donh ? 410 s v s = 13.2 v, resistive load of 12 ? high-side off t doffh ? 0.6 1 s low-side on t donl ? 23.5 s low-side off t doffl ? 2.5 4 s output switching times (device not in stand-by for t > 1 ms) high-side switch rise time t rise h ? 1.8 3.5 s v s = 13.2 v, resistive load of 12 ? high-side switch fall time t fall h ? 0.2 0.8 s low-side switch rise time t rise l 25.510 s low-side switch fall time t fall l 24.36.5 s note: for switching time definitions, see figure 6 . 3.3 electrical characteristics (cont ? d) 8 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test conditions min. typ. max.
tle 6209 r preliminary data sheet, version 2.0 18 2001-03-14 inhibit input h-input voltage threshold v iinhh ?? 0.7 v cc ? l-input voltage threshold v iinhl 0.2 ?? v cc ? hysteresis of input voltage v iinhhy 50 300 500 mv ? pull down current (low) i iinhl 10 25 50 a v iinh = 0.2 v cc pull down current (high) i iinhh ?? t.b.d. a v iinh = 0.7 v cc disable input h-input voltage threshold v idish ?? 0.7 v cc ? l-input voltage threshold v idisl 0.2 ?? v cc ? hysteresis of input voltage v idishy 50 300 500 mv ? pull up current (high) i idish ? 50 ? 25 ? 10 a v idis = 0.7 v cc pull up current (low) i idisl ? 50 ?? a v idis = 0.2 v cc direction/pwm input h-input voltage threshold v ih ?? 0.7 v cc ? l-input voltage threshold v il 0.2 ?? v cc ? hysteresis of input voltage v ihy 50 300 500 mv ? input current i i ? 20 2 a v i = 0.7 v cc 3.3 electrical characteristics (cont ? d) 8 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test conditions min. typ. max.
tle 6209 r preliminary data sheet, version 2.0 19 2001-03-14 spi-interface delay time from stand-by to data in/power on reset setup time t set ?? 100 s ? logic inputs sdi, sclk and csn h-input voltage threshold v ih ?? 0.7 v cc ? l-input voltage threshold v il 0.2 ?? v cc ? hysteresis of input voltage v ihy 50 300 500 mv ? pull up current at pin csn (high) i icsnh ? 50 ? 25 ? 10 a v csn = 0.7 v cc pull up current at pin csn (low) i icsnl ? 50 ?? a v csn = 0.2 v cc pull down current at pin sdi and sclk (low) i isdil ( i isclkl ) 10 25 50 a v sdi ( v sclk ) = 0.2 v cc pull down current at pin sdi and sclk (high) i isdih ( i isclkh ) ?? 50 a v sdi ( v sclk ) = 0.7 v cc input capacitance at pin csn, sdi or sclk c i ? 10 15 pf 0 v < v cc < 5.25 v note: input capacitances are guaranteed by design. 3.3 electrical characteristics (cont ? d) 8 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test conditions min. typ. max.
tle 6209 r preliminary data sheet, version 2.0 20 2001-03-14 logic output sdo h-output voltage level v sdoh v cc ? 1.0 v cc ? 0.85 ? v i sdoh =1 ma l-output voltage level v sdol ? 0.25 0.4 v i sdol = ? 1.6 ma tri-state leakage current i sdolk ? 10 ? 10 a v csn = v cc 0v < v sdo < v cc tri-state input capacitance c sdo ? 10 15 pf v csn = v cc 0v< v cc < 5.25 v note: input capacitances are guaranteed by design. 3.3 electrical characteristics (cont ? d) 8 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test conditions min. typ. max.
tle 6209 r preliminary data sheet, version 2.0 21 2001-03-14 serial data input timing serial clock period t psclk 500 ? ? ns ? serial clock high time t sclkh 250 ? ? ns ? serial clock low time t sclkl 250 ? ? ns ? serial clock low before csn low t bef 250 ? ? ns ? csn setup time t lead 250 ? ? ns ? sclk setup time t lag 250 ? ? ns ? clock low after csn high t beh 250 ? ? ns ? sdi setup time t sdisu 125 ? ? ns ? sdi hold time t sdiho 125 ? ? ns ? input signal rise time at pin sdi, sclk and csn t rsin ? ? 100 ns ? input signal fall time at pin sdi, sclk and csn t fsin ? ? 100 ns ? serial data output timing sdo rise time t rsdo ? 25 50 ns c l = 100 pf sdo fall time t fsdo ? 25 50 ns c l = 100 pf sdo enable time t ensdo ? ? 125 ns low impedance sdo disable time t dissdo ? ? 125 ns high impedance sdo valid time t vasdo ? 50 125 ns v do < 0.2 v cc ; v do > 0.7 v cc ; c l = 100 pf 3.3 electrical characteristics (cont ? d) 8 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test conditions min. typ. max.
tle 6209 r preliminary data sheet, version 2.0 22 2001-03-14 note: temperature thresholds are guaranteed by design. thermal prewarning, warning and shutdown thermal prewarning junction temperature t jpw 120 140 160 c ? temperature prewarning hysteresis ? t ? 20 ? k ? thermal warning junction temperature t jw 140 160 180 c ? temperature prewarning hysteresis ? t ? 20 ? k ? thermal shutdown junction temperature t jsd 160 180 200 c ? temperature shutdown hysteresis ? t ? 20 ? k ? ratio of w to pw temperature t jw / t jpw 1.07 1.14 ??? ratio of sd to w temperature t jsd / t jpw 1.06 1.13 ??? 3.3 electrical characteristics (cont ? d) 8 v < v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test conditions min. typ. max.
tle 6209 r preliminary data sheet, version 2.0 23 2001-03-14 4diagrams figure 4 switch-off time during current limitation (chopper off-time) figure 5 short circuit of high-side switch to gnd t off_xx 9v v out 0 13.2v v 9v i out gnd out vs vs t dsd 0 5v v i out pwm i sdh i sc
tle 6209 r preliminary data sheet, version 2.0 24 2001-03-14 figure 6 output delay and switching time definitions figure 7 standard data transfer timing 90% 10% t d1 t rise t fall 50% 50% t d2 v out pwm input 0 5 v 10% 90% 100% dir = l / h => v out = v out 1/2 resistive load to vs => t rise = t rise l , t fall = t fall l t d1 = t d off l , t d2 = t d on l resistive load to gnd => t rise = t rise h , t fall = t fall h t d1 = t d on h , t d2 = t d off h 3 0 7 3 24 1 sdi sclk csn 0 7 6 5 4 3 2 1 sdo csn high to low & rising edge of sclk: sdo is enabled. status information is transfered to output shift register csn low to high: data from shift-register is transfered to output driver logic previous status actual data sdi: data will be accepted on the falling edge of clk-signal sdo: state will change on the rising edge of clk-signal __ _ _ _ _ _ _ time 0 0 0 + new data actual status actual data old data 1 2 0 7 6 5 4 56
tle 6209 r preliminary data sheet, version 2.0 25 2001-03-14 figure 8 timing for error detection only figure 9 spi-input timing sdi sclk csn 0 sdo csn high to low & sclk stays low: status information of data bit 0 ( error flag ) is transfered to sdo sdi: data is not accepted sdo: status information of data bit 0 ( error-flag ) will stay as long as csn is low time _ tristate tristate t sclkl t lag t beh t lead t bef sclk csn 0.7 v cc 0.2 v cc 0.7 v cc 0.2 v cc sdi 0.7 v cc 0.2 v cc t sclkh t sdiho t sdisu dont care valid dont care valid dont care
tle 6209 r preliminary data sheet, version 2.0 26 2001-03-14 figure 10 do valid data delay time and valid time figure 11 sdo enable and disable time t vasdo sdo sclk 0.7 v cc 0.2 v cc 0.7 v cc 0.2 v cc 50 % t rsdo ( low to high ) t rsin t fsin sdo 0.7 v cc 0.2 v cc ( high to low ) t fsdo csn 0.7 v cc 0.2 v cc 50 % t fsin t rsin sdo t ensdo 50 % t dissdo sdo t ensdo 50 % t dissdo 10 k ? pullup to v cc 10 k ? pulldown to gnd
tle 6209 r preliminary data sheet, version 2.0 27 2001-03-14 5 application figure 12 application circuit bias 8 bit logic and latch inhibit charge pump s p i uv ov tsd fault- detect 1 v cc inh sclk sdo sdi csn drv direct input pwm dir v s gnd out 2 out 1 dis driver & gate-control wd gnd micro- controller for ems/etc function r v cc micro-controller for evaluation process monitoring gnd m 16 15 4,17 2,3 18,19 14 13 7 5 6 8 12 9 tle 4278g c d 10nf d i q reset watchdog c q 22f c drv 33nf z39 100f v bat gnd 100nf
tle 6209 r preliminary data sheet, version 2.0 28 2001-03-14 6 package outlines p-dso-20-12 (plastic dual small outline package) +0.07 -0.02 -0.3 1.2 2.8 1.3 0.25 1) does not include plastic or metal protrusion of 0.15 max. per side 20x 0.25 m 1) heatsink 0.95 14.2 +0.15 index marking 15.9 10 1 0.1 +0.13 0.4 1.27 3.5 max. 0 6.3 11 3.25 20 11 ?.15 ?.1 ?.15 1 x 45? ?.3 5? ?? ?.15 15.74 ?.1 a a 1) b 0.25 m b gps05791 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information . dimensions in mm smd = surface mounted device

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